1. Technical Field
The present invention relates to a control circuit of a semiconductor device having an over-heat protecting function suitable for preventing, due to an over-heat, a damage of a semiconductor element for a large electric power used for driving, for instance, a lamp of a motor vehicle.
2. Background Art
As the control circuit of a semiconductor device having an over-heat protecting function, JP-B-3585105 discloses a device that can reduce a possibility of breaking the semiconductor device. This device includes, as shown in FIG. 6, a CPU 1, an amplifying circuit 2, a semiconductor device 3 having an over-heat protecting function for turning on/off a driving of a load 4 and an output state detecting part 5.
The CPU 1 internally generates (or fetches from an external signal source not shown in the drawing) a control signal for controlling the semiconductor device 3 having the over-heat protecting function, for instance, a PWM (Pulse Width Modulation) control signal and outputs the control signal from an output port P1. The amplifying circuit 2 is a push-pull type amplifying circuit including a plurality of transistors and a plurality of resistances.
The semiconductor device 3 having the over-heat protecting function includes a MOSFET 3a of N ch, a gate resistance 3b connected between the gate of the MOSFET 3a and a gate terminal G, a temperature detecting circuit 3c connected between the source of the MOSFET 3a and a source terminal S, a latch circuit 3d for latching a temperature detecting output of the temperature detecting circuit 3c and a gate interrupting circuit 3e connected between the gate and the source of the MOSFET 3a and controlled by the output of the latch circuit 3d. The above-described circuits and the members are mounted on one chip.
The drain of the MOSFET 3a is connected to a drain terminal D connected to a +B power source and the source is connected to the source terminal S. Then, the over-heat protecting function of the semiconductor device 3 is realized by the cooperation of the gate resistance 3b, the temperature detecting circuit 3c, the latch circuit 3d and the gate interrupting circuit 3e. 
The load 4 designates, for instance, a lamp used for a winker (a flasher) showing a turn signal in a vehicle. The output state detecting part 5 supplies a detected output of an output state to an input port P2 of the CPU 1.
In the above-described structure, when the PWM control signal outputted from the output port P1 of the CPU 1 is amplified in the amplifying circuit 2, and supplied to the gate of the MOSFET 3a to carry out a PWM control, the CPU 1 detects, through the output state detecting part 5, the output voltage of the MOSFET 3a, that is, a source voltage of the MOSFET 3a relative to the continuous rise and fall of the PWM control signal at a monitoring timing at intervals of a rise time tG (ON)+a prescribed time ts (in this case, ts<tG (OFF)−tG (ON)).
At this time, when the state of the load 4 is normal, the source voltage rises at each rise time tG (ON) of the gate voltage of the MOSFET 3a by the PWM control signal, and falls at each fall time tG (OFF), so that the source voltage has the same wave form as that of the gate voltage. Accordingly, when the CPU 1 detects a source output state in accordance with a detecting output from the output state detecting part 5 at the monitoring timing of tG (ON)+ts from each rise, Hi (that is, a logic 1) is obtained.
On the other hand, when an abnormality, for instance, a short-circuit arises in the load 4, the MOSFET 3a is over-heat interrupted by the cooperation of the temperature detecting circuit 3c, the latch circuit 3d and the gate interrupting circuit 3e. Thus, the source voltage of the MOSFET 3a has wave forms falling at timings gradually shorter from the rise time tG(ON) of the gate voltage every protecting operation. Accordingly, when the CPU 1 detects a source output state in accordance with a detecting output from the output state detecting part 5 at the monitoring timing of tG (ON)+ts from each rise, Lo (that is, a logic 0) is obtained.
Then, when the CPU 1 detects that the source output state is Lo (that is, a logic 0) continuously m times or for n seconds at each monitoring timing, the CPU 1 does not supply the PWM control signal to the output port P1 to stop the PWM control of the MOSFET 3a. The above-described m times or the n seconds are set to the number of times or a time that can sufficiently avoid the MOSFET 3a from being broken. As a result, a current is not supplied between the drain and the source of the MOSFET 3a to prevent the damage of the MOSFET 3a due to the rise of a temperature.
In JP-B-3585105, when the abnormality such as the short-circuit arises in the load 4, and the MOSFET 3a is over-heat interrupted by the cooperation of the temperature detecting circuit 3c, the latch circuit 3d and the gate interrupting circuit 3e, the CPU 1 detects that the source output state obtained through the output state detecting part 5 is Lo (that is, a logic 0) continuously m times or for n seconds at each monitoring timing to stop the PWM control of the MOSFET 3a for the purpose of a protecting operation. Therefore, a problem arises that a circuit is complicated and enlarged.
Further, when it is decided whether or not the protecting operation is carried out, an operation that the MOSFET 3a is turned on again to be over-heat interrupted needs to be repeated several times. Thus, a problem also arises that the deterioration of the MOSFET 3a may possibly advance.
Further, a vehicle has a load 4 such as a hazard lamp that is driven not only when an ignition switch is turned on, but also when the ignition switch is turned off. A circuit structure in this case is shown in, for instance, FIG. 7.
FIG. 7 shows the structure that a power circuit 6 and a PWM turning on switch 7 for turning on the load 4 such as the hazard lamp are added to the circuit structure shown in FIG. 6. In FIG. 7, a CPU 1 and the power circuit 6 are turned off so as not to consume an electric power when the ignition switch not shown in the drawing is turned off. Here, when the ignition switch is turned off, if the PWM turning on switch 7 is turned on, the electric power from the power circuit 6 is supplied to the CPU 1 and an amplifying circuit 2 so that the load 4 is driven by the PWM control of the CPU 1.
In such a structure, when an abnormal state arises, for instance, the load 4 is short-circuited, a MOSFET 3a is over-heat interrupted by the cooperation of a temperature detecting circuit 3c, a latch circuit 3d and a gate interrupting circuit 3e. At this time, as shown in a timing chart of FIG. 8, the source voltage of the MOSFET 3a has wave forms falling at timings gradually shorter from the rise time of the gate voltage every protecting operation.
Then, the CPU 1 detects that a source output state obtained through an output state detecting part 5 is Lo (that is, a logic 0) continuously m times or for n seconds to stop the PWM control of the MOSFET 3a. After the PWM control is stopped, when the PWM turning on switch 7 is turned on/off, the operation of the CPU 1 is reset by turning off a power source.
When the operation of the CPU 1 is reset as described above, an over-heat interrupting operation is repeated in such a way that while the temperature of the MOSFET 3a is high, the load 4 is driven again by the PWM control from the CPU 1, then, an over-heat interruption is immediately carried out, or while an over-heat protecting operation is detected, the PWM turning on switch 7 is turned off and then, turned on again. Thus, a problem arises that the MOSFET 3a may be possibly broken.